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1 typical application circuit appears at end of data sheet. 19-6384; rev 0; 6/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX9273.related . general description the MAX9273 compact serializer is designed to drive 50 i coax or 100 i shielded twisted-pair (stp) cable. the device pairs with the max9272 deserializer. the parallel input is programmable for single or double input. double input allows higher pixel clock input frequency by registering two pixels of typical image-sensor video data before serializing. this doubles the maximum pixel clock frequency compared to single input. the device features an embedded control channel that operates at 9.6kbps to 1mbps in uart and mixed uart/ i 2 c modes, and up to 400kbps in i 2 c mode. using the control channel, a microcontroller ( f c) is capable of programming serializer, deserializer, and camera (or any peripheral) registers at any time, independent of video timing. there is one dedicated gpio, four optional gpios, and a gpo output, allowing remote power-up of a camera module, camera frame synchronization, and other uses. error-detection and correction coding are programmable. for driving longer cables, the serializer has program - mable pre/deemphasis. programmable spread spectrum is available on the serial output. the serial output meets iso 10605 and iec 61000-4-2 esd standards. the core supply range is 1.7v to 1.9v and the i/o supply range is 1.7v to 3.6v. the device is available in a 40-pin (6mm x 6mm) tqfn-ep package with 0.5mm lead pitch and oper - ates over the -40 n c to +105 n c temperature range. applications automotive camera systems navigation displays benefits and features s ideal for camera applications ? drives low-cost 50 i coax cable and fakra connectors or 100 i stp ? error detection/correction ? 9.6kbps to 1mbps control channel in i 2 c-to-i 2 c mode with clock stretch capability ? best-in-class supply current: 75ma (max) ? double-rate clock for megapixel cameras ? serializer pre/deemphasis allows 15m cable at full speed ? 40-pin (6mm x 6mm) tqfn package with 0.5mm lead pitch s high-speed data serialization for megapixel cameras ? up to 1.5gbps serial-bit rate with single or double input: 6.25mhz to 100mhz clock s multiple control-channel modes for system flexibility ? 9.6kbps to 1mbps control channel in uart-to- uart or uart-to-i 2 c modes s reduces emi and shielding requirements ? output programmable for 100mv to 500mv single-ended or 100mv to 400mv differential ? programmable spread spectrum on the serial output reduces emi ? bypassable input pll for parallel clock jitter attenuation ? tracks spread spectrum on parallel input s peripheral features for camera power-up and verification ? built-in prbs generator for ber testing of the serial link ? up to five gpio ports ? dedicated up/down gpo for camera frame sync trigger and other uses s reduces power requirements ? remote/local wake-up from sleep mode s meets rigorous automotive and industrial requirements ? -40 n c to +105 n c operating temperature ? 8kv contact and 15kv air iso 10605 and iec 61000-4-2 esd protection MAX9273 22-bit gmsl serializer with coax or stp cable drive evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
2 MAX9273 22-bit gmsl serializer with coax or stp cable drive table of contents general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 absolute maximum ratings ...................................................................... 6 package thermal characteristics .................................................................. 6 dc electrical characteristics ..................................................................... 6 typical operating characteristics ................................................................ 10 pin configuration ............................................................................. 11 pin description ............................................................................... 11 functional diagram ........................................................................... 13 detailed description ........................................................................... 18 register mapping ........................................................................... 18 input bit map ............................................................................... 18 serial link signaling and data format ........................................................... 23 reverse control channel ..................................................................... 23 data-rate selection ......................................................................... 23 control channel and register programming ...................................................... 23 uart interface ............................................................................. 23 interfacing command-byte-only i 2 c devices with uart .......................................... 26 uart bypass mode ....................................................................... 26 i 2 c interface ............................................................................... 27 start and stop conditions ................................................................ 27 bit transfer .............................................................................. 27 acknowledge ............................................................................ 27 slave address ........................................................................... 29 bus reset ............................................................................... 29 format for writing ......................................................................... 29 format for reading ....................................................................... 30 i 2 c communication with remote-side devices ................................................. 30 i 2 c address translation ...................................................................... 30 control-channel broadcast mode .............................................................. 31 gpo/gpi control ............................................................................ 31 pre/deemphasis driver ....................................................................... 31 spread spectrum ........................................................................... 31 manual programming of the spread-spectrum divider .............................................. 32 additional error detection and correction ........................................................ 33 cyclic redundancy check (crc) ............................................................ 33
3 MAX9273 22-bit gmsl serializer with coax or stp cable drive table of contents ( continued ) hamming code .......................................................................... 33 hs/vs encoding and/or tracking ............................................................... 33 serial output ............................................................................... 34 coax-mode splitter .......................................................................... 34 configuration inputs (conf1, conf0) ........................................................... 34 sleep mode ................................................................................ 35 power-down mode .......................................................................... 35 configuration link ........................................................................... 37 link startup procedure ......................................................................... 37 applications information ........................................................................ 37 prbs test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 error generator ............................................................................. 37 dual c control ............................................................................. 37 jitter-filtering pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 pclkin spread tracking ..................................................................... 37 changing the clock frequency ................................................................ 37 fast detection of loss-of-synchronization ........................................................ 37 providing a frame sync (camera applications) .................................................... 38 software programming of the device addresses ................................................... 38 three-level configuration inputs ............................................................... 38 configuration blocking ....................................................................... 38 compatibility with other gmsl devices .......................................................... 38 gpios .................................................................................... 38 internal input pulldowns ...................................................................... 39 choosing i 2 c/uart pullup resistors ............................................................ 39 ac-coupling ............................................................................... 39 selection of ac-coupling capacitors ............................................................ 39 power-supply circuits and bypassing ........................................................... 39 power-supply table .......................................................................... 39 cables and connectors ...................................................................... 39 board layout ............................................................................... 40 esd protection ............................................................................. 40 typical application circuit ...................................................................... 48 ordering information .......................................................................... 48 chip information .............................................................................. 48 package information ........................................................................... 48 revision history .............................................................................. 49
4 MAX9273 22-bit gmsl serializer with coax or stp cable drive list of figures figure 1. serial-output parameters ............................................................... 14 figure 2. output waveforms at out+, out- ........................................................ 14 figure 3. single-ended output template ........................................................... 14 figure 4. worst-case pattern input ............................................................... 14 figure 5. parallel clock input requirements ........................................................ 15 figure 6. i 2 c timing parameters ................................................................. 15 figure 7. differential output template ............................................................. 15 figure 8. input setup and hold times ............................................................. 16 figure 9. gpi-to-gpo delay ..................................................................... 16 figure 10. serializer delay ...................................................................... 17 figure 11. link startup time ..................................................................... 17 figure 12. power-up delay ...................................................................... 18 figure 13. single-input waveform (latch on rising edge of pclkin selected) ............................. 22 figure 14. single-input function block ............................................................ 22 figure 15. double-input function block ............................................................ 22 figure 16. double-input waveform (latch on rising edge of pclkin selected) ............................ 23 figure 17. serial-data format .................................................................... 24 figure 18. gmsl uart protocol for base mode ..................................................... 25 figure 19. gmsl uart data format for base mode ................................................. 25 figure 20. sync byte (0x79) .................................................................... 25 figure 21. ack byte (0xc3) ..................................................................... 25 figure 22. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) ........ 26 figure 23. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) ........ 27 figure 24. start and stop conditions ........................................................... 28 figure 25. bit transfer ......................................................................... 28 figure 26. acknowledge ....................................................................... 28 figure 27. slave address ....................................................................... 29 figure 28. format for i 2 c write .................................................................. 29 figure 29. format for write to multiple registers ..................................................... 29 figure 30. format for i 2 c read .................................................................. 30 figure 31. 2:1 coax-mode splitter connection diagram ............................................... 34 figure 32. coax-mode connection diagram ........................................................ 34 figure 33. state diagram, all applications ......................................................... 36 figure 34. human body model esd test circuit ..................................................... 40 figure 35. iec 61000-4-2 contact discharge esd test circuit ......................................... 40 figure 36. iso 10605 contact discharge esd test circuit ............................................. 40
5 MAX9273 22-bit gmsl serializer with coax or stp cable drive list of tables table 1. power-up default register map (see table 15) ............................................... 19 table 2. input map ............................................................................ 21 table 3. data-rate selection table ............................................................... 24 table 4. i 2 c bit-rate ranges .................................................................... 30 table 5. tp/coax drive current (cmllvl = 1000) ................................................... 31 table 6. serial output spread ................................................................... 32 table 7. spread limitations ..................................................................... 32 table 8. modulation coefficients and maximum sdiv settings .......................................... 33 table 9. configuration input map ................................................................. 34 table 10. startup procedure for video-display applications ............................................ 35 table 11. startup procedure for image-sensing applications ........................................... 36 table 12. MAX9273 feature compatibility .......................................................... 38 table 13. typical power-supply currents (using worst-case input pattern) ................................ 39 table 14. suggested connectors and cables for gmsl ............................................... 39 table 15. register table (see table 1) ............................................................. 41
6 MAX9273 22-bit gmsl serializer with coax or stp cable drive avdd to ep .......................................................... -0.5v to +1.9v dvdd to ep .......................................................... -0.5v to +1.9v iovdd to ep ......................................................... -0.5v to +3.9v out+, out- to ep ............................................... -0.5v to +1.9v all other pins to ep .............................. -0.5v to (v iovdd + 0.5v) out+, out- short circuit to ground or supply ........ continuous * ep connected to pcb ground. continuous power dissipation (t a = +70 n c) tqfn (derate 37mw/ n c above +70 n c) ..................... 2963mw junction temperature ..................................................... +150 n c operating temperature range ........................ -40 o c to +105 n c storage temperature range ............................ -65 o c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c tqfn junction-to-ambient thermal resistance ( q ja ) .......... 27c/w junction-to-case thermal resistance ( q jc ) ..................... 1c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) dc electrical characteristics (v avdd = v dvdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 i 1% (differential), ep connected to pcb ground (gnd), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 1.8v, t a = +25 n c.) * parameter symbol conditions min typ max units single-ended inputs (din_, hs, vs, ms, pwdn , drs, autos , pclkin) high-level input voltage v ih1 0.65 x v iovdd v low-level input voltage v il1 0.35 x v iovdd v input current i in1 v in = 0v to v iovdd -10 +20 f a three-level logic inputs (conf0, conf1) high-level input voltage v ih 0.7 x v iovdd v low-level input voltage v il 0.3 x v iovdd v midlevel input current i inm (note 2) -10 +10 f a input current i in -150 +150 f a single-ended output (gpo) high-level output voltage v oh1 i out = -2ma v iovdd - 0.2 v low-level output voltage v ol1 i out = 2ma 0.2 v output short-circuit current i os v o = 0v v iovdd = 3.0v to 3.6v 16 35 64 ma v iovdd = 1.7v to 1.9v 3 12 21
7 MAX9273 22-bit gmsl serializer with coax or stp cable drive dc electrical characteristics (continued) (v avdd = v dvdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 i 1% (differential), ep connected to pcb ground (gnd), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 1.8v, t a = +25 n c.) parameter symbol conditions min typ max units open-drain inputs/outputs (rx/sda, tx/scl, gpio_) high-level input voltage v ih2 0.7 x v iovdd v low- level input voltage v il2 0.3 x v iovdd v input current i in2 (note 3) rx/sda, tx/scl -110 +1 f a gpio_ -80 +1 low-level output voltage v ol2 i out = 3ma v iovdd = 1.7v to 1.9v 0.4 v v iovdd = 3.0v to 3.6v 0.3 differential serial outputs (out+, out-) differential output voltage v od preemphasis off (figure 1) 300 400 500 mv 3.3db preemphasis setting (figure 2) 350 610 3.3db deemphasis setting (figure 2) 240 425 change in v od between complementary output states d v od 25 mv output offset voltage (v out+ + v out- )/2 = v os v os preemphasis off 1.1 1.4 1.56 v change in v os between complementary output states d v os 25 mv output short-circuit current i os v out+ or v out- = 0v -62 ma v out+ or v out- = 1.9v 25 magnitude of differential output short-circuit current i osd v od = 0v 25 ma output termination resistance (internal) r o from v out+ , v out- to v avdd 45 54 63 i single-ended serial outputs (out+, out-) single-ended output voltage v od preemphasis off, high drive (figure 3) 375 500 625 mv 3.3db preemphasis setting, high drive (figure 2) 435 765 3.3db deemphasis setting, high drive (figure 2) 300 535 output short-circuit current i os v out+ or v out- = 0v -69 ma v out+ or v out- = 1.9v 32 output termination resistance (internal) r o from v out+ or v out- to v avdd 45 54 63 i
8 MAX9273 22-bit gmsl serializer with coax or stp cable drive dc electrical characteristics (continued) (v avdd = v dvdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 i 1% (differential), ep connected to pcb ground (gnd), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v av dd = v dvdd = v iovdd = 1.8v, t a = +25 n c.) ac electrical characteristics (v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), ep connected to pcb ground (gnd), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 1.8v, t a = +25 n c) parameter symbol conditions min typ max units reverse control-channel receiver outputs (out+, out-) high switching threshold v chr 27 mv low switching threshold v clr -27 mv power supply worst-case supply current (figure 4) i wcs single input, bws = 0 f pclkin = 25mhz 40 65 ma f pclkin = 50mhz 50 75 double input, bws = 0 f pclkin = 50mhz 40 65 f pclkin = 100mhz 51 75 sleep mode supply current i ccs single wake-up receiver enabled 40 100 f a power-down supply current i ccz pwdn = ep 5 70 f a esd protection out+, out- (note 4) v esd human body model, r d = 1.5k i , c s = 100pf 8 kv iec 61000-4-2, r d = 330 i , c s = 150pf contact discharge 10 air discharge 15 iso 10605, r d = 2k i , c s = 330pf contact discharge 10 air discharge 30 all other pins (note 5) v esd human body model, r d = 1.5k i , c s = 100pf 4 kv parameter symbol conditions min typ max units clock input (pclkin) clock frequency f pclkin bws = 1, drs = 1 6.25 12.5 mhz bws = 0, drs = 1 8.33 16.66 bws = 1, drs = 0 12.5 37.5 bws = 0, drs = 0 16.66 50 bws = 1, drs = 0, 15-bit double input 25 75 bws = 0, drs = 0, 11-bit double input 33.33 100 clock duty cycle dc _ t high /t t or t low /t t (figure 5, note 6) 35 50 65 % clock transition time t r , t f_ (figure 5, note 6) 4 ns clock jitter t j 1.5gbps bit rate, 300khz sinusoidal jitter 800 ps (pk-pk)
9 MAX9273 22-bit gmsl serializer with coax or stp cable drive note 2: to provide a midlevel, leave the input open, or, if driven, put driver in high impedance. high-impedance leakage current must be less than q 10a. note 3: i in min due to voltage drop across the internal pullup resistor. note 4: specified pin to ground. note 5: specified pin to all supply/ground. note 6: guaranteed by design and not production tested. note 7: measured in serial link bit times. bit time = 1/(30 x f pclkin) for bws = 0. bit time = 1/(40 x f pclkin ) for bws = 1. ac electrical characteristics (continued) (v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), ep connected to pcb ground (gnd), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 1.8v, t a = +25 n c) parameter symbol conditions min typ max units i 2 c/uart and gpio port timing i 2 c/uart bit rate 9.6 1000 kbps output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k i pullup to iovdd 20 120 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k i pullup to iovdd 20 120 ns input setup time t set i 2 c only (figure 6, note 6) 100 ns input hold time t hold i 2 c only (figure 6, note 6) 0 ns switching characteristics (n ote 6) differential output rise/fall time t r , t f 20% to 80%, v od r 400mv r l = 100 i , serial-bit rate = 1.5gbps 250 ps total serial output jitter (differential output) t tsoj1 1.5gbps prbs signal, measured at v od = 0v differential, preemphasis disabled (figure 7) 0.25 ui deterministic serial output jitter (differential output) t dsoj2 1.5gbps prbs signal, measured at v od = 0v differential, preemphasis disabled (figure 7) 0.15 ui total serial output jitter (single-ended output) t tsoj1 1.5gbps prbs signal, measured at v o /2, preemphasis disabled (figure 3) 0.25 ui deterministic serial output jitter (single-ended output) t dsoj2 1.5gbps prbs signal, measured at v o /2, preemphasis disabled (figure 3)1.5gbps prbs signal 0.15 ui parallel data input setup time t set (figure 8) 2 ns parallel data input hold time t hold (figure 8) 1 ns gpi-to-gpo delay t gpio_ deserializer gpi to serializer gpo (figure 9) 350 f s serializer delay (note 7) t sd (figure 10) spread spectrum enabled 6880 bits spread spectrum disabled 3040 link start time t lock (figure 11) 2 ms power-up time t pu (figure 12) 7 ms
10 typical operating characteristics (v avdd = v dvdd = v iovdd = 1.8v, dbl = low, t a = +25 n c, unless otherwise noted.) supply current vs.pclkin frequency (bws = 0) MAX9273 toc01 pclkin frequency (mhz) supply current (ma) 40 45 35 30 25 20 15 10 40 45 50 55 60 65 70 35 55 0 prbs on, coax mode preemphasis = 0x0b to 0x0f preemphasis = 0x01 to 0x04 preemphasis = 0x00 output power spectrum vs. pclkin frequency (various spread) MAX9273 toc04 pclkin frequency (mhz) output power spectrum (dbm) 52 51 50 49 48 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 47 53 f pclkin = 50mhz 0% spread 1% spread 4% spread 0.5% spread 2% spread maximum pclkin frequency vs. stp cable length (ber 10 -10 ) MAX9273 toc07 stp cable length (m) pclkin frequency (mhz) 15 10 5 20 40 60 optimum pe /e q settings 6db pe, eq off no pe, 10.7db eq no pe, eq off ber can be as low as 10 -12 for cable lengths less than 10m 0 02 0 supply current vs. pclkin frequency (bws = 1) MAX9273 toc02 pclkin frequency (mhz) supply current (ma) 35 30 25 20 15 10 40 45 50 55 60 65 70 35 54 0 prbs on, coax mode preemphasis = 0x0b to 0x0f preemphasis = 0x01 to 0x04 preemphasis = 0x00 serial link switching pattern with 6db preemphasis (parallel bit rate = 50mhz, 10m stp cable) MAX9273 toc05 50mv/div 200ps/div 1.5gbps maximum pclkin frequency vs. coax cable length (ber 10 -10 ) MAX9273 toc08 coax cable length (m) pclkin frequency (mhz) 15 20 10 5 20 40 60 0 02 5 6db pe, eq off no pe, 10.7db eq no pe, eq off ber can be as low as 10 -12 for cable lengths less than 10m output power spectrum vs. pclkin frequency (various spread) MAX9273 toc03 pclkin frequency (mhz) output power spectrum (dbm) 21.0 20.5 20.0 19.5 19.0 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 18.5 21.5 f pclkin = 20mhz 0.5% spread 1% spread 2% spread 0% spread 4% spread serial link switching pattern with 6db preemphasis (parallel bit rate = 50mhz, 20m coax cable) MAX9273 toc06 50mv/div 200ps/div 1.5gbps additional differential load capacitance (pf) pclkin frequency (mhz) 8 6 4 2 10 20 30 40 50 60 0 01 0 maximum pclkin frequency vs. additional differential c l (ber < 10 -10 ) MAX9273 toc09 6db pe, eq off 10m stp cable optimum pe /e q settings no pe, 10.7db eq no pe, eq off ber can be as low as 10 -12 for c l < 4pf for optimum pe / eq settings MAX9273 22-bit gmsl serializer with coax or stp cable drive
11 MAX9273 22-bit gmsl serializer with coax or stp cable drive pin description pin configuration pin name function 1, 2, 3, 5C8, 16, 17, 32, 33, 34, 36, 37, 38 din0Cdin13, din20, din21 parallel data inputs with internal pulldown to ep 4, 27 avdd 1.8v analog power supply. bypass avdd to ep with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller capacitor closest to avdd. 9C12 din14/ gpio2Cdin17/ gpio5 parallel data inputs/gpio. defaults to parallel data input on power-up. parallel data input has internal pulldown to ep. gpio_ has an open-drain output with internal 60k i pullup to iovdd. see register table for programming details. 13 din18/hs parallel data input/horizontal sync with internal pulldown to ep. defaults to parallel data input on power-up. horizontal sync input when vs/hs encoding is enabled (table 2). 14 din19/vs parallel data input/vertical sync with internal pulldown to ep. defaults to parallel data input on power-up. vertical sync input when vs/hs encoding is enabled (table 2). tqfn (6mm x 6mm x 0.75mm) connect ep to ground plane MAX9273 top view 35 36 34 33 12 11 13 din8 avdd din10 din11 din12 14 din7 avdd out- conf1 rx / sda tx / scl conf0 drs 12 din2 45 67 27 28 29 30 26 24 23 22 dvdd din3 gpo din21 din20 iovdd din9 out+ 3 25 37 din4 din19/v s 38 39 40 din5 iovdd ep* din6 din18/v s din17/ gpio5 din16/ gpio4 + din1 32 15 gpio1 din0 31 16 17 18 19 20 ms din13 din14/ gpio2 din15/ gpio3 89 10 21 pclkin autos pwdn
12 MAX9273 22-bit gmsl serializer with coax or stp cable drive pin description (continued) pin name function 15, 39 iovdd i/o supply voltage. 1.8v to 3.3v logic i/o power supply. bypass iovdd to ep with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smallest value capacitor closest to iovdd. 18 gpo general-purpose output. gpo follows the gmsl deserializer gpi (or int) input. gpo = low upon power-up and when pwdn = low. 19 gpio1 open-drain, general-purpose input/output with internal 60k i pullup to iovdd 20 ms mode-select input with internal pulldown to ep. set ms = low to select base mode. set ms = high to select bypass mode. 21 pwdn active-low, power-down input with internal pulldown to ep. set pwdn low to enter power-down mode to reduce power consumption. 22 drs data-rate select input with internal pulldown to ep (table 15). 23 conf0 configuration 0. three-level configuration input (table 9). 24 conf1 configuration 1. three-level configuration input (table 9). 25 out- inverting coax/twisted-pair serial output 26 out+ noninverting coax/twisted-pair serial output 28 rx/sda uart receive or i 2 c serial-data input/output with internal 30k i pullup to iovdd. in uart mode, rx/sda is the rx input of the serializers uart. in the i 2 c mode, rx/sda is the sda input/output of the serializers i 2 c master/slave. rx/sda has an open-drain driver and requires a pullup resistor. 29 tx/scl uart transmit or i 2 c serial-clock input/output with internal 30k i pullup to iovdd. in uart mode, tx/scl is the tx output of the serializers uart. in the i 2 c mode, tx/scl is the scl input/output of the serializers i 2 c master/slave. tx/scl has an open-drain driver and requires a pullup resistor. 30 autos autostart input with internal pulldown to ep. autos = low enables serialization upon power- up and automatic frequency range selection of pclkin. autos = high puts the part in sleep mode upon power-up. 31 pclkin parallel clock input with internal pulldown to ep. latches parallel data inputs and provides the pll reference clock. 35 dvdd 1.8v digital power supply. bypass dvdd to ep with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller value capacitor closest to dvdd. ep exposed pad. ep is internally connected to device ground. must connect ep to the pcb ground plane through an array of vias for proper thermal and electrical performance.
13 MAX9273 22-bit gmsl serializer with coax or stp cable drive functional diagram single -/ double- input latch fifo fcc scramble / crc / hamming / 8b /10b encode parallel to seria l uart/i 2 c tx /scl rx /sda clkdiv sspll filter pll gpio din15/gpio3 din16/gpio4 din17/gpio5 gpo gpio1 out+ out- din18/hs din19/vs reverse control channel cml tx rx din14/gpio2 pclkin din0 ?din13 MAX9273 din20, din21
14 MAX9273 22-bit gmsl serializer with coax or stp cable drive figure 1. serial-output parameters figure 2. output waveforms at out+, out- figure 4. worst-case pattern input figure 3. single-ended output template out- v od v os gnd r l /2 r l /2 out+ out- out+ (out+) - (out-) v os(-) v os(+) ((out+) + (out-))/2 v os(-) v od(-) v od(-) v od = 0v dv os = |v os(+) - v os(-) | dv od = |v od(+) - v od(-) | v od (+) out+ out- v os v od(p) v od(d) serial-bit time out+ or out- v o /2 v o /2 v o v o pclkin note: pclkin programmed for rising latch edge. din_
15 MAX9273 22-bit gmsl serializer with coax or stp cable drive figure 5. parallel clock input requirements figure 6. i 2 c timing parameters figure 7. differential output template v il max t high t low t t t r t f v ih min pclkin protocol scl sda start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) t su;sta t low t high t buf t hd;sta t r t sp t f t su;dat t hd;dat t vd;dat t vd;ack t su;sto 1/f scl 800mv p-p t tsoj1 2 t tsoj1 2
16 MAX9273 22-bit gmsl serializer with coax or stp cable drive figure 8. input setup and hold times figure 9. gpi-to-gpo delay v ih min v ih min v ih min v il max v il max v il max pclkin din_ t hold t set note: pclkin programmed for rising latching edge. t gpio t gpio v oh_min v ol_max v ih_min v il_max deserializer gpi serializer gpo
17 MAX9273 22-bit gmsl serializer with coax or stp cable drive figure 10. serializer delay figure 11. link startup time serial link inactive serial link active channel disabled reverse control channel disabled t lock 350fs pclkin reverse control channel available pwdn must be high t sd first bit last bit n n+3 expanded time scale n+4 n n+1 n+2 n-1 din_ pclkin out+/-
18 MAX9273 22-bit gmsl serializer with coax or stp cable drive figure 12. power-up delay detailed description the MAX9273 serializer, when paired with the max9272 deserializer, provides the full set of operating features, but offers basic functionality when paired with any gmsl deserializer. the serializer has a maximum serial-bit rate of 1.5gbps for 15m or more of cable and operates up to a maximum input clock of 50mhz in 22-bit, single-input mode, or 75mhz/100mhz in 15-bit/11-bit, double-input mode, respectively. pre/deemphasis, along with the gmsl deserializer channel equalizer, extends the link length and enhances link reliability. the control channel enables a f c to program serial - izer and deserializer registers and program registers on peripherals. the f c can be located at either end of the link, or at both ends. two modes of control-channel operation are available with associated protocols and data formats. base mode uses either i 2 c or gmsl uart, while bypass mode uses a user-defined uart. spread spectrum is available to reduce emi on the serial output. the serial output complies with iso 10605 and iec 61000-4-2 esd protection standards. register mapping registers set the operating conditions of the serializer and are programmed using the control channel in base mode. the serializer holds its device address and the device address of the deserializer it is driving. similarly, the driven deserializer holds its device address and the address of the serializer by which it is driven. whenever a device address is changed, be sure to write the new address to both devices. the default device address of the MAX9273 serializer (or any gmsl serializer) is 0x80 and the default device address of any gmsl deserial - izer is 0x90 ( table 1 ). registers 0x00 and 0x01 in both devices hold the device addresses. input bit map the parallel input functioning and width depends on settings of the double-/single-input mode (dbl), hs/vs encoding (hven), error correction (edc), and bus width (bws). dina are the inputs latched by the pixel clock in single-input mode, or the inputs latched on the first pixel clock in double-input mode. dinb are the inputs latched on the second pixel clock in double-input mode. table 2 lists the bit map for the control pin settings. pwdn powered down v ih1 t pu reverse control channel disabled 350s pclkin powered up, serial link inactive powered up, serial link active reverse control channel enabled reverse control channel enabled reverse control channel disabled
19 MAX9273 22-bit gmsl serializer with coax or stp cable drive table 1. power-up default register map (see table 15 ) register address (hex) power-up default (hex) power-up default settings (msb first) 0x00 0x80 serid = 1000000, serializer device address cfgblock = 0, registers 0x00 to 0x1f are read/write 0x01 0x90 desid = 1001000, deserializer device address reserved = 0 0x02 0x1f ss = 000, no spread spectrum reserved = 1 prng = 11, automatically detect the pixel clock range srng = 11, automatically detect serial-data rate 0x03 0x00 autofm = 00, calibrate spread-modulation rate only once after locking sdiv = 000000, auto calibrate sawtooth divider 0x04 0x07, 0x87 seren = 0 ( autos = high), seren = 1( autos = low), serial link enable default depends on autos pin state at power-up clinken = 0, configuration link disabled prbsen = 0, prbs test disabled sleep = 0, sleep mode disabled (see the link startup procedure section) inttype = 01, local control channel uses uart revccen = 1, reverse control channel active (receiving) fwdccen = 1, forward control channel active (sending) 0x05 0x01 i2cmethod = 0, i 2 c packets include register address enjitfilt = 0, jitter filter disabled prbslen = 00, continuous prbs length reserved = 00 enwaken = 0, out- wake-up receiver disabled enwakep = 1, out+ wake-up receiver enabled 0x06 0x80, 0xa0 cmllvl = 1000 or 1010, output level determined by the state of conf1, conf0 at power-up preemp = 0000, preemphasis disabled 0x07 0x00, 0x10 dbl = 0, double-input mode drs = 0, high data-rate mode bws = 0, 24-bit mode es = 0 or 1, edge-select input setting determined by the state of conf1, conf0 at startup reserved = 0 hven = 0, hs/vs encoding disabled edc = 00, 1-bit parity error detection 0x08 0x00 invvs = 0, serializer does not invert vsync invhs = 0, serializer does not invert hsync reserved = 000000 0x09 0x00 i2csrca = 0000000, i 2 c address translator source a is 0x00 reserved = 0
20 MAX9273 22-bit gmsl serializer with coax or stp cable drive table 1. power-up default register map (see table 15 ) (continued) register address (hex) power-up default (hex) power-up default settings (msb first) 0x0a 0x00 i2cdsta = 0000000, i 2 c address translator destination a is 0x00 reserved = 0 0x0b 0x00 i2csrcb = 0000000, i 2 c address translator source b is 0x00 reserved = 0 0x0c 0x00 i2cdstb = 0000000, i 2 c address translator destination b is 0x00 reserved = 0 0x0d 0xb6 i2clocack = 1, acknowledge generated when forward channel is not available i2cslvsh = 01, 469ns/234ns i 2 c setup/hold time i2cmstbt = 101, 339kbps (typ) i 2 c-to-i 2 c master bit-rate setting i2cslvto = 10, 1024 f s (typ) i 2 c-to-i 2 c slave remote timeout 0x0e 0x42 dis_rev_p = 0, out+ reverse channel receiver enabled dis_rev_n = 1, out- reverse channel receiver disabled gpio5en = 0, gpio5 disabled gpio4en = 0, gpio4 disabled gpio3en = 0, gpio3 disabled gpio2en = 0, gpio2 disabled gpio1en = 1, gpio1 enabled reserved = 0 0x0f 0xfe reserved = 11 gpio5out = 1, gpio5 set high gpio4out = 1, gpio4 set high gpio3out = 1, gpio3 set high gpio2out = 1, gpio2 set high gpio1out = 1, gpio1 set high setgpo = 0, gpo set low 0x10 0x3e reserved = 00 gpio5in = 1, gpio5 is input high gpio4in = 1, gpio4 is input high gpio3in = 1, gpio3 is input high gpio2in = 1, gpio2 is input high gpio1in = 1, gpio1 is input high gpo_l = 0, gpo set low 0x11 0x00 errgrate = 00, generate an error every 2560 bits errgtype = 0, generate single-bit errors errgcnt = 00, continuously generate errors errgper = 0, disable periodic error generation errgen = 0, disable error generation 0x12 0x40 reserved = 01000000 0x13 0x22 reserved = 00100010 0x14 0xxx reserved = xxxxxxxx
21 MAX9273 22-bit gmsl serializer with coax or stp cable drive table 1. power-up default register map (see table 15 ) (continued) table 2. input map x = dont care. * in double-input mode (dbl = 1), dina are latched on the first cycle of pclkin and dinb are latched on the second cycle of pclkin. edc bws dbl hven dina dinb* serial link word bits 0 0 0 0 0:21 0:21 0 0 0 1 0:17, 20:21, hs, vs 0:17, 20:21 0 0 1 0 0:10 0:10 0:21 0 0 1 1 0:10, hs, vs 0:10, hs, vs 0:21 0 1 0 0 0:21 0:21 0 1 0 1 0:17, 20:21, hs, vs 0:17, 20:21 0 1 1 0 0:14 0:14 0:29 0 1 1 1 0:14, hs, vs 0:14, hs, vs 0:29 1 0 0 0 0:15 0:15 1 0 0 1 0:15, hs, vs 0:15 1 0 1 0 0:7 0:7 0:15 1 0 1 1 0:7, hs, vs 0:7, hs, vs 0:15 1 1 0 0 0:21 0:21 1 1 0 1 0:17, 20:21, hs, vs 0:17, 20:21 1 1 1 0 0:11 0:11, hs, vs 0:23 1 1 1 1 0:11, hs, vs 0:11, hs, vs 0:23 register address (hex) power-up default (hex) power-up default settings (msb first) 0x15 0x00 cxtp = 0, cxtp is low i2csel = 0, input is low lccen = 0, local control channel disabled reserved = 000 outputen = 0, output disabled pclkdet = 0, no valid pclkin detected 0x16 0xxx (read only) reserved = xxxxxxxx 0x17 0xxx (read only) reserved = xxxxxxxx 0x1e 0x0b (read only) id = 00001011, device id is 0x0b 0x1f 0x0x (read only) reserved = 000 caps = 0, serializer is not hdcp capable revision = xxxx, revision number
22 MAX9273 22-bit gmsl serializer with coax or stp cable drive the parallel input has two input modes: single- and double-rate input. in single-input mode, latch a stores data from din_ every pclkin cycle ( figure 13 ). parallel data from latch a is then sent to the scrambler for serialization ( figure 14 ). the device accepts pixel clocks from 6.25mhz to 50mhz. in double-input mode, latch b stores two input words ( figure 15 ). data from latch b is sent to the scrambler as a combined word. the max9272 deserializer outputs the combined word (single-output mode) or two half-sized words (double-output mode). the serializer/deserializer use pixel clock rates from 33.3mhz to 100mhz for 11-bit, double-input mode and 25mhz to 75mhz for 15-bit, double-input mode. see figure 16 for timing details. figure 13. single-input waveform (latch on rising edge of pclkin selected) figure 14. single-input function block figure 15. double-input function block first word first word pclkin din0?din21 latch a second word second word third word third word fourth word fourth word din0?din21 input latch a pclkin MAX9273 pclkin din0?din14 or din0?din10 input latch b input latch b 2 MAX9273
23 MAX9273 22-bit gmsl serializer with coax or stp cable drive figure 16. double-input waveform (latch on rising edge of pclkin selected) serial link signaling and data format the serializer uses differential cml signaling to drive twisted-pair cable and single-ended cml to drive coaxial cable. the output amplitude is programmable. input data is scrambled and then 8b/10b coded. the deserializer recovers the embedded serial clock, then samples, decodes, and descrambles the data. in 24-bit or 32-bit mode, 22 or 30 bits contain the video data and/or error correction bits, if used. the 23rd or 31st bit carries the forward control-channel data. the last bit is the parity bit of the previous 23 or 31 bits ( figure 17 ). reverse control channel the serializer uses the reverse control channel to receive i 2 c/uart and gpo signals from the deserializer in the opposite direction of the video stream. the reverse control channel and forward video data coexist on the same serial cable forming a bidirectional link. the reverse control channel operates independently from the forward control channel. the reverse control channel is available 2ms after power-up. the serializer temporarily disables the reverse control channel for 350 f s after start - ing/stopping the forward serial link. data-rate selection the serializer/deserializer use drs, dbl, and bws to set the pclkin frequency range ( table 3 ). set drs = 1 for a pclkin frequency range of 6.25mhz to 12.5mhz (32- bit, single-input mode) or 8.33mhz to 16.66mhz (24-bit, single-input mode). set drs = 0 for normal operation. it is not recommended to use double-input mode when drs = 1. control channel and register programming the control channel is available for the f c to send and receive control data over the serial link simultaneously with the high-speed data. the f c controls the link from either the serializer or deserializer side. the control chan - nel between the f c and serializer or deserializer runs in base mode or bypass mode, according to the mode- selection (ms) input of the device connected to the f c. base mode is a half-duplex control channel and bypass mode is a full-duplex control channel. uart interface in base mode, the f c is the host and can access the registers of both the serializer and deserializer from either side of the link using the gmsl uart protocol. the f c can also program the peripherals on the remote side by sending the uart packets to the serializer or deserializer, with the uart packets converted to i 2 c by the device on the remote side of the link. the f c communicates with a uart peripheral in base mode (through inttype register settings), using the half-duplex default gmsl uart protocol of the serializer/deserial - izer. the device addresses of the serializer/deserializer in base mode are programmable. the default value is 0x80 for the serializer and 0x90 for the deserializer. when the peripheral interface is i 2 c, the serializer/ deserializer convert uart packets to i 2 c that have device addresses different from those of the serializer or deserializer. the converted i 2 c bit rate is the same as the original uart bit rate. first word second word third word fourth word first word third word first and second word third and fourth word pclkin 2 latch a latch b din0?din14 or din0?din10
24 MAX9273 22-bit gmsl serializer with coax or stp cable drive the deserializer uses differential line coding to send signals over the reverse channel to the serializer. the bit rate of the control channel is 9.6kbps to 1mbps in both directions. the serializer/deserializer automatically detect the control-channel bit rate in base mode. packet bit-rate changes can be made in steps of up to 3.5 times higher or lower than the previous bit rate. see the changing the clock frequency section for more informa - tion on changing the control-channel bit rate. figure 19 shows the uart data format. figure 20 and figure 21 detail the formats of the sync byte (0x79) and the ack byte (0xc3). the f c and the connected slave chip generate the sync byte and ack byte, respectively. events such as device wake-up and gpi generate transitions on the control channel that can be ignored by the f c. data written to the serializer/deserial - izer registers do not take effect until after the acknowl - edge byte is sent. this allows the f c to verify that write commands are received without error, even if the result of the write command directly affects the serial link. the slave uses the sync byte to synchronize with the host uarts data rate. if the gpi or ms/hven inputs of the deserializer toggle while there is control-channel com - munication, or if a line fault occurs, the control-channel communication is corrupted. in the event of a missed or delayed acknowledge (~1ms due to control-channel timeout), the f c should assume there was an error in the packet when the slave device received it, or that an error occurred during the response from the slave device. in base mode, the f c must keep the uart tx/rx lines high for 16 bit times before starting to send a new packet. figure 17. serial-data format table 3. data-rate selection table drs setting dbl setting bws setting pclkin range (mhz) 0 0 (single input) 0 (24-bit mode) 16.66 to 50 0 0 1 (32-bit mode) 12.5 to 35 0 1 (double input) 0 33.3 to 100 0 1 1 25 to 75 1 0 0 8.33 to 16.66 1 0 1 6.25 to 12.5 1 1 0 do not use 1 1 1 do not use d0 d1 d21 fcc pcb d0 d1 d29 fcc pcb forward control- channel bi t packe t parit y check bi t note: serial data shown before scrambling and 8b /10b encoding video and error- correction data 24 bits 32 bits forward control- channel bi t packet parit y check bi t video and error- correction data
25 MAX9273 22-bit gmsl serializer with coax or stp cable drive figure 18. gmsl uart protocol for base mode figure 19. gmsl uart data format for base mode figure 20. sync byte (0x79) figure 21. ack byte (0xc3) start d0 11000011 d1 d2 d3 d4 d5 d6 d7 parity stop write data format sync dev addr + r/w reg addr number of bytes sync dev addr + r/w reg addr number of bytes byte 1 byte n ack byte n byte 1 ack master reads from slave read data format master writes to slave master writes to slave master reads from slave start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 1 uart frame frame 1 frame 2 frame 3 stop start stop start start d0 10011110 d1 d2 d3 d4 d5 d6 d7 parity stop
26 MAX9273 22-bit gmsl serializer with coax or stp cable drive as shown in figure 22 , the remote-side device converts packets going to or coming from the peripherals from uart format to i 2 c format and vice versa. the remote device removes the byte number count and adds or receives the ack between the data bytes of i 2 c. the i 2 c bit rate is the same as the uart bit rate. interfacing command-byte-only i 2 c devices with uart the serializer/deserializer uart-to-i 2 c conversion can interface with devices that do not require register address - es, such as the max7324 gpio expander. in this mode, the i 2 c master ignores the register address byte and directly reads/writes the subsequent data bytes ( figure 23 ). change the communication method of the i 2 c master using the i2cmethod bit. i2cmethod = 1 sets command-byte- only mode, while i2cmethod = 0 sets normal mode where the first byte in the data stream is the register address. uart bypass mode in bypass mode, the serializer/deserializer ignore uart commands from the f c and the f c communicates with the peripherals directly using its own defined uart pro - tocol. the f c cannot access the serializer/deserializer registers in this mode. peripherals accessed through the forward control channel using the uart interface need to handle at least one pclkin period q 10ns of jitter due to the asynchronous sampling of the uart signal by pclkin. set ms = high to put the control channel into bypass mode. for applications with the f c connected to the deserializer, there is a 1ms wait time between setting ms high and the bypass control channel being active. there is no delay time when switching to bypass mode when the f c is connected to the serializer. do not send a logic-low value longer than 100 f s to ensure proper gpo functionality. bypass mode accepts bit rates down to 10kbps in either direction. see the gpo/gpi control section for gpo functionality limitations. the control- channel data pattern should not be held low longer than 100 f s if gpo control is used. figure 22. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) 11 sync frame register address number of bytes device id + wr data 0 dev id a 11 11 11 11 data n 11 11 s 1 1 1 ack frame 7 : master to slave 8 serializer/deserializer peripheral w 1 reg addr 8 a 11 81 11 sync frame register address number of bytes device id + rd 11 11 11 11 ack frame data 0 11 data n 11 uart-to-i 2 c conversion of write packet (i2cmethod = 0) uart-to-i 2 c conversion of read packet (i2cmethod = 0) s: start p: stop a: acknowledge : slave to master data 0a data na p dev id a s 11 7 w 1 dev id a s 11 7 r 1 data np 1 8 a 1 data 0 8 a 1 reg addr 8 a 1 fc serializer/deserializer fc serializer/deserializer serializer/deserializer peripheral
27 MAX9273 22-bit gmsl serializer with coax or stp cable drive i 2 c interface in i 2 c-to-i 2 c mode, the serializer control-channel inter - face sends and receives data through an i 2 c-compatible 2-wire interface. the interface uses a serial-data line (sda) and a serial-clock line (scl) to achieve bidirec - tional communication between master and slave(s). a f c master initiates all data transfers to and from the device and generates the scl clock that synchronizes the data transfer. when an i 2 c transaction starts on the local-side devices control-channel port, the remote-side devices control-channel port becomes an i 2 c master that inter - faces with remote-side i 2 c peripherals. the i 2 c master must accept clock stretching that is imposed by the seri - alizer (holding scl low). the sda and scl lines operate as both an input and an open-drain output. pullup resis - tors are required on sda and scl. each transmission consists of a start condition ( figure 6 ) sent by a mas - ter, followed by the devices 7-bit slave address plus a r/ w bit, a register address byte, one or more data bytes, and finally a stop condition. start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmission with a start (s) condition by transitioning sda from high to low while scl is high ( figure 24 ). when the master has finished communicating with the slave, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. bit transfer one data bit is transferred during each clock pulse ( figure 25 ). the data on sda must remain stable while scl is high. acknowledge the acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data ( figure 26 ). thus, each byte transferred effectively requires nine bits. the master generates the 9th clock pulse, and the recipi - ent pulls down sda during the acknowledge clock pulse. the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the slave device, the slave device generates the acknowledge bit figure 23. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) : master to slave serializer/deserializer serializer/deserializer serializer /deserializer uart-to-i 2 c conversion of read packet (i2cmethod = 1) uart-to-i 2 c conversion of write packet (i2cmethod = 1) fc serializer /deserializer fc sync frame 11 11 11 11 11 11 11 11 11 11 11 11 11 11 device id + rd register address number of bytes sync frame device id + wr register address number of bytes data 0d ata na ck frame ack frame data 0d ata n data n a data 0 wa dev id s ap peripheral peripheral s 11 18 88 1 1 1 17 11 8 11 1 7 dev id ra aa p data 0d ata n : slave to master s: start p: stop a: acknowledge
28 MAX9273 22-bit gmsl serializer with coax or stp cable drive figure 24. start and stop conditions figure 25. bit transfer figure 26. acknowledge scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 1 2 8 9 s sda scl start condition stop condition s p sda scl data line stable; data valid change of data allowed
29 MAX9273 22-bit gmsl serializer with coax or stp cable drive because the slave device is the recipient. when the slave device is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. the device generates an acknowledge even when the forward control channel is not active (not locked). to pre - vent acknowledge generation when the forward control channel is not active, set the i2clocack bit low. slave address the serializer/deserializer have a 7-bit-long slave address. the bit following a 7-bit slave address is the r/ w bit, which is low for a write command and high for a read command. the slave address is 10000001 for read com - mands and 10000000 for write commands. see figure 27 . bus reset the device resets the bus with the i 2 c start condition for reads. when the r/ w bit is set to 1, the serializer/ deserializer transmit data to the master, thus the master is reading from the device. format for writing a write to the serializer/deserializer comprises the trans - mission of the slave address with the r/ w bit set to zero, followed by at least one byte of information. the first byte of information is the register address or command byte. the register address determines which register of the device is to be written by the next byte, if received. if a stop (p) condition is detected after the register address is received, the device takes no further action figure 27. slave address figure 28. format for i 2 c write figure 29. format for write to multiple registers sda 0 ack scl msb lsb 1 0r /w 00 00 s 1 0 0 0 address = 0x80 0 = write 0 0 0 0 a 0 0 0 0 register address = 0x00 0 0 0 0 a p d7 d6 d5 d4 register 0x00 write data d3 d2 d1 d0 a s = start bit p = stop bit a = ack d_ = data bit s = start bit p = stop bit a = ack n = nack d_ = data bit s 1 0 0 0 address = 0x80 0 = write 0 0 0 0 a 0 0 0 0 register address = 0x00 0 0 0 0 a d7 d6 d5 d4 register 0x00 write data d3 d2 d1 d0 ad 7 p d6 d5 d4 register 0x01 write data d3 d2 d1 d0 n
30 MAX9273 22-bit gmsl serializer with coax or stp cable drive beyond storing the register address ( figure 28 ). any bytes received after the register address are data bytes. the first data byte goes into the register selected by the register address, and subsequent data bytes go into subsequent registers ( figure 29 ). if multiple data bytes are transmitted before a stop condition, these bytes are stored in subsequent registers because the register addresses autoincrement. format for reading the serializer/deserializer are read using the internally stored register address as an address pointer, the same way the stored register address is used as an address pointer for a write. the pointer autoincrements after each data byte is read using the same rules as for a write. thus, a read is initiated by first configuring the register address by performing a write ( figure 30 ). the master can now read consecutive bytes from the device, with the first data byte being read from the register address pointed by the previously written register address. once the master sends a nack, the device stops sending valid data. i 2 c communication with remote-side devices the serializer supports i 2 c communication with a periph - eral on the remote side of the communication link using scl clock stretching. while multiple masters can reside on either side of the communication link, arbitration is not provided. the connected masters need to support scl clock stretching. the remote-side i 2 c bit-rate range must be set according to the local-side i 2 c bit rate. supported remote-side bit rates can be found in table 4 . set the i2cmstbt (register 0x0d) to set the remote i 2 c bit-rate. if using a bit rate different than 400kbps, local- and remote- side i 2 c setup and hold times should be adjusted by set - ting the slv_sh register settings on both sides. i 2 c address translation the serializer supports i 2 c address translation for up to two device addresses. use address translation to assign unique device addresses to peripherals with limited i 2 c addresses. source addresses (address to translate from) are stored in registers 0x09 and 0x0b. destination addresses (address to translate to) are stored in registers 0x0a and 0x0c. figure 30. format for i 2 c read table 4. i 2 c bit-rate ranges local bit rate remote bit-rate range i2cmstbt setting f > 50kbps up to 1mbps any 20kbps > f > 50kbps up to 400kbps up to 110 f < 20kbps up to 10kbps 000 s = start bit p = stop bit a = ack n = nack d_ = data bit s s 1 0 0 0 address = 0x80 0 = write 0 0 0 0 a 1 = read repeated start 0 0 0 0 register address = 0x00 0 0 0 0 a 1 0 0 0 address = 0x81 0 0 0 1 ad 7 p d6 d5 d4 register 0x00 read data d3 d2 d1 d0 n
31 MAX9273 22-bit gmsl serializer with coax or stp cable drive control-channel broadcast mode the serializer supports broadcast commands to control multiple peripheral devices. select an unused device address to use as a broadcast device address. program the remote-side gmsl device to translate the broadcast device address (source address stored in registers 0x09, 0x0b) to the peripheral device address (destination address stored in register 0x0a, 0x0c). any commands sent to the broadcast address are sent to all designated peripherals, while commands sent to a peripherals unique device address are sent to that particular device only. gpo/gpi control gpo on the serializer follows gpi transitions on the dese - rializer. this gpo/gpi function can be used to transmit signals such as frame sync in a surround-view camera system. the gpi-to-gpo delay is 0.35ms (max). keep time between gpi transitions to a minimum 0.35ms. this includes transitions from the other deserializer in the coax-mode splitter. bit d4 of register 0x0e in the deserial - izer stores the gpi input state. gpo is low after power-up. the f c can set gpo by writing to the set_gpo register bit. do not send a logic-low value on the serializer rx/ sda input (uart mode) longer than 100 f s in either base or bypass mode to ensure proper gpo/gpi functionality. pre/deemphasis driver the serial line driver employs current-mode logic (cml) signaling. the driver is differential when programmed for twisted-pair cable. when programmed for coax, one side of the cml driver is used. the line driver has pro - grammable pre/deemphasis that modifies the output to compensate for cable length. there are 13 preemphasis settings, as shown in table 5 . negative preemphasis levels are deemphasis levels where the preemphasized swing level is the same as normal swing, but the no- transition data (e.g., a 1 followed by a 1) is deempha - sized. program the preemphasis levels through register 0x06 d[3:0] of the serializer. this preemphasis function compensates the high-frequency loss of the cable and enables reliable transmission over longer link distances. current drive for both tp and coax modes is program - mable. cmllvl bits (0x06, d[7:4]) program drive current in tp and coax modes for single-ended voltage swings from 100mv to 500mv. spread spectrum to reduce the emi generated by the transitions on the serial link, the serializer output is programmable for spread spectrum. if the deserializer driven by the serial - izer has programmable spread spectrum, do not enable spread for both at the same time or their interaction table 5. tp/coax drive current (cmllvl = 1000) * negative preemphasis levels denote deemphasis. preemphasis level (db)* preemp setting (0x06, d[3:0]) i cml (ma) i pre (ma) single-ended voltage swing max (mv) min (mv) -6.0 0100 12 4 400 200 -4.1 0011 13 3 400 250 -2.5 0010 14 2 400 300 -1.2 0001 15 1 400 350 0 (power-on default) 0000 16 0 400 400 1.1 1000 16 1 425 375 2.2 1001 16 2 450 350 3.3 1010 16 3 475 325 4.4 1011 16 4 500 300 6.0 1100 15 5 500 250 8.0 1101 14 6 500 200 10.5 1110 13 7 500 150 14.0 1111 12 8 500 100
32 MAX9273 22-bit gmsl serializer with coax or stp cable drive cancels benefits. the deserializer tracks the serializers spread and passes the spread to the deserializer output. the programmable spread-spectrum amplitudes are q 0.5%, q 1%, q 1.5%, q 2%, q 3%, and q 4% ( table 6 ). some spread-spectrum amplitudes can only be used at lower pclkin frequencies ( table 7 ). there is no pclkin frequency limit for the q 0.5% spread rate. when the spread spectrum is turned on or off, the serial link stops for several microseconds and then restarts in order for the deserializer to lose and relock to the new serial-data stream. the serializer includes a sawtooth divider to control the spread-modulation rate. autodetection of the pclkin operation range guarantees a spread-spectrum modu - lation frequency within 20khz to 40khz. additionally, manual configuration of the sawtooth divider (sdiv: 0x03, d[5:0]) allows the user to set a modulation frequency according to the pclkin frequency. when ranges are manually selected, program the sdiv value for a fixed modulation frequency around 20khz. manual programming of the spread-spectrum divider the modulation rate relates to the pclkin frequency as follows: pclkin m f f (1 drs) mod x sdiv = + where: f m = modulation frequency drs = drs value (0 or 1) f pclkin = pclkin frequency mod = modulation coefficient given in table 8 sdiv = 6-bit sdiv setting, manually programmed by the f c to program the sdiv setting, first look up the modula - tion coefficient according to the desired bus-width and spread-spectrum settings. solve the above equation for sdiv using the desired pixel clock and modulation fre - quencies. if the calculated sdiv value is larger than the maximum allowed sdiv value in table 8 , set sdiv to the maximum value. table 6. serial output spread table 7. spread limitations ss spread (%) 000 no spread spectrum. power-up default. 001 0.5% spread spectrum. 010 1.5% spread spectrum. 011 2% spread spectrum. 100 no spread spectrum. 101 1% spread spectrum. 110 3% spread spectrum. 111 4% spread spectrum. bws = 0 mode, pclkin frequency (mhz) bws = 1 mode pclkin frequency (mhz) serial link bit rate (mbps) available spread rates < 33.3 (dbl=0) < 25 (dbl = 0) < 1000 all rates available < 66.6 (dbl = 1) < 50 (dbl = 1) 33.3 to 50 (dbl = 0) 25 to 37.5 (dbl = 0) r 1000 1.5%, 1.0%, 0.5% 66.6 to 100 (dbl = 1) 50 to 75 (dbl = 1)
33 MAX9273 22-bit gmsl serializer with coax or stp cable drive table 8. modulation coefficients and maximum sdiv settings additional error detection and correction in default mode (additional error detection and correction disabled), data encoding/decoding is the same as in pre - vious gmsl serializers/deserializers (parity only). at the serializer, the parallel input word is scrambled and a par - ity bit added. the scrambled word is divided into 3 or 4 bytes (depending on the bws setting), 8b/10b encoded, and then transmitted serially. at the deserializer, the same operations are performed in reverse order. the parity bit is used by the deserializer to find the word boundary and for error detection. errors are counted in an error counter register and an error pin indicates errors. the serializer can use of of two additional error-detection/ correction methods (selectable by register setting): 1) 6-bit cyclic redundancy check 2) 6-bit hamming code with 16-word interleaving cyclic redundancy check (crc) when crc is enabled, the serializer adds 6 bits of crc to the input data. this reduces the available bits in the input data word by 6, compared to the non-crc case (see table 2 for details). for example, 16 bits are available for input data instead of 22 bits when bws = 0, and 24 bits instead of 30 bits when bws = 1. the crc generator polynomial is x 6 + x + 1 (as used in the itu-t g704 telecommunication standard). the parity bit is still added when crc is enabled, because it is used for word-boundary detection. when crc is enabled, each data word is scrambled and then the 6-bit crc and 1-bit parity are added before the 8b/10b encoding. at the deserializer, the crc code is recalculated. if the recalculated crc code does not match the received crc code, an error is flagged. this crc error is reported to the error counter. hamming code hamming code is a simple and effective error-correction code to detect and/or correct errors. the MAX9273 seri - alizer (when used with the max9272 gmsl deserializer) uses single-error correction/double-error detection per pixel hamming-code scheme. the serializer uses data interleaving for burst-error toler - ance. burst errors up to 11 consecutive bits on the serial link are corrected, and burst errors up to 31 consecutive bits are detected. hamming code adds overhead similar to crc. see table 2 for details regarding the available input word size. hs/vs encoding and/or tracking hs/vs encoding by a gmsl serializer allows horizontal and vertical synchronization signals to be transmitted while conserving pixel data bandwidth. with hs/vs encoding enabled, 10-bit pixel data with a clock up to 100mhz can be transmitted using 1 pixel of data per hs/ vs transition, versus 8-bit data with a clock up to 100mhz without hs/vs encoding. the deserializer performs hv decoding, tracks the period of the hv signals, and uses voting to filter hs/vs bit errors. when using hv encod - ing, use a minimum low-pulse duration of two pclkin cycles when dbl = 0 on the max9271/MAX9273. when dbl = 1, use a minimum hs/vs low-pulse duration of five pclkin cycles and a minimum high-pulse duration of two pclkin cycles. when using hamming code and hs/vs encoding, do not send more than two transitions every 16 pclkin cycles. when the serializer uses double-input mode (dbl = 1), the active duration, plus the blanking duration of hs or vs signals, should be an even number of pclkin cycles. if hs/vs tracking is used without hv encoding, use din0 for hsync and din1 for vsync. in this case, if dbl values on the serializer and the deserializer are different, set the deserializers uneqdbl register bit to 1. if the bws spread- spectrum setting (%) modulation coefficient (dec) sdiv upper limit (dec) 1 1 104 40 0.5 104 63 3 152 27 1.5 152 54 4 204 15 2 204 30 0 1 80 52 0.5 80 63 3 112 37 1.5 112 63 4 152 21 2 152 42
34 MAX9273 22-bit gmsl serializer with coax or stp cable drive serializer and deserializer have unequal dbl settings and hven = 0, then hs/vs inversion should only be used on the side that has dbl = 1. hs/vs encoding sends packets when hsync or vsync is low, use hs/vs inver - sion register bits if the input hsync and vsync signals use an active-low convention to send data packets dur - ing the inactive pixel clock periods. serial output the driver output is programmable for two types of cable: 100 i twisted pair and 50 i coax (contact the factory for serializers with 75 i cable drive). coax-mode splitter in coax mode, out+ and out- are active. this enables use as a 1:2 splitter ( figure 31 ). in coax mode, connect out+ to in+ of the deserializer. connect out- to in- of the second deserializer. control-channel data is broad - cast from the serializer to both deserializers and their attached peripherals. assign a unique device address to send control data to one deserializer. leave all unused in_ pins unconnected, or connect them to ground through 50 i and a capacitor for increased power-supply rejection. if out- is not used, connect out- to avdd through a 50 i resistor ( figure 32 ). when there are f cs at the serializer, and at each deserializer, only one f c can communicate at a time. disable one splitter control- channel link to prevent contention. use the dis_rev_p or dis_rev_n register bits to disable a control-channel link. configuration inputs (conf1, conf0) conf1 and conf0 determine the power-up values of the serial output type, the input data latch, and the control- channel interface type ( table 9 ). these functions can be changed after power-up by writing to the appropriate register bits figure 31. 2:1 coax-mode splitter connection diagram figure 32. coax-mode connection diagram table 9. configuration input map conf1 conf0 cxtp (out+/out- output type) es (pclkin latch edge) i2csel (control-channel type) low low 1 (coax) 1 (falling) 1 (i 2 c-to-i 2 c) low mid 1 (coax) 1 (falling) 0 (uart-to-i 2 c/uart) low high 1 (coax) 0 (rising) 1 (i 2 c-to-i 2 c) mid low 1 (coax) 0 (rising) 0 (uart-to-i 2 c/uart) mid mid 0 (stp) 1 (falling) 1 (i 2 c-to-i 2 c) mid high 0 (stp) 1 (falling) 0 (uart-to-i 2 c/uart) high low 0 (stp) 0 (rising) 1 (i 2 c-to-i 2 c) high mid 0 (stp) 0 (rising) 0 (uart-to-i 2 c/uart) high high do not use do not use do not use out+ out- in+ in- in+ in- gmsl deserializer gmsl deserializer MAX9273 out+ out- in+ in- avdd 50i gmsl deserializer MAX9273
35 MAX9273 22-bit gmsl serializer with coax or stp cable drive sleep mode the serializer includes a sleep mode to reduce power consumption. the device enters or exits sleep mode by a command from a local f c or a remote f c using the control channel. set the sleep bit to 1 to initiate sleep mode. the serializer sleeps immediately after setting its sleep = 1. the out+ and out- serial outputs each have wake-up receiver to accept wake-up commands from the attached deserializers. on power-up, the out+ wake-up receiver is enabled and the out- wake-up receiver is disabled. disable the wake-up receivers (through enwakep or enwaken) if the devices are disconnected or wake-up is not used in order to reduce sleep-mode current. if both wake-up receivers are disabled, the device can only be woken up from the local control channel. to wake up the device, send an arbitrary control-channel command to the serializer. wait 5ms for the chip to power up and then write 0 to the sleep register bit to make the wake-up permanent. power-down mode the serializer has a power-down mode that further reduc - es power consumption compared to sleep mode. set pwdn low to enter power-down mode. in power-down mode, the serial outputs are in high impedance. entering power-down resets the devices registers. upon exiting power-down, the state of the ms, drs, conf0, conf1, and autos pins are latched. table 10. startup procedure for video-display applications no. c serializer deserializer f c connected to serializer. sets all configuration inputs. if any configuration inputs are available on one end of the link but not on the other, always connects that configuration input low. sets all configuration inputs. if any configuration inputs are available on one end of the link but not on the other, always connects that configuration input low. 1 powers up. powers up and loads default settings. powers up and loads default settings. 2 enables configuration link by setting clinken = 1 (if not enabled automatically) and gets an acknowledge. waits for link to be established (~3ms). establishes configuration link. locks to configuration link signal. 3 writes one link configuration bit (drs, bws, or edc) in the deserializer and gets an acknowledge. configuration changed from default settings (loss-of-lock occurs if bws or edc changes). 4 writes corresponding serializer link configuration bit and gets an acknowledge. configuration changed from default settings. relocks to configuration link signal. 5 waits for link to be established (~3ms) and then repeats steps 3 through 4 until all serial link bits are configured. 6 writes remaining configuration bits in the serializer/deserializer and gets an acknowledge. configuration changed from default settings. configuration changed from default settings. 7 enables video link by setting seren = 1 and gets an acknowledge. waits for link to be established (~3ms). begins serializing data. locks to serial link signal and begins deserializing data.
36 MAX9273 22-bit gmsl serializer with coax or stp cable drive figure 33. state diagram, all applications table 11. startup procedure for image-sensing applications no. c serializer deserializer f c connected to deserializer. sets all configuration inputs. if any inputs are available on one chip but not on the other, always connects input low. sets all configuration inputs. if any inputs are available on one chip but not on the other, always connects input low. 1 powers up. powers up and loads default settings. establishes serial link. powers up and loads default settings. locks to serial link signal. 3 writes deserializer configuration bits and gets an acknowledge. configuration changed from default settings (loss-of-lock occurs if bws or edc changes). 4 writes serializer configuration bits. does not get an acknowledge (or gets a dummy acknowledge) if loss-of-lock occurred. configuration changed from default settings. relocks to serial link signal. 5 enables video link by setting seren = 1 (if not enabled automatically). cannot get an acknowledge (or gets a dummy acknowledge) if loss-of-lock occurred. waits for link to be established (~3ms). begins serializing data. locks to serial link signal and begins deserializing data. low high 1 0 seren power-up value seren = 0 for > 8ms video link operating video link prbs test wake-up sleep = 1 wake-up signal config link started clinken = 0 or seren = 1 clinken = 1 unlocked locked config link config link sleep = 0, sleep power-on idle power-off all states pwdn = low or sleep = 1 power-down or power-off autos = low pwdn = high, power-on video link locking autos pin setting config link operating program registers clinken = 0 or seren = 1 video link locked video link unlocked prbsen = 0 prbsen = 1 seren = 1, pclkin running seren = 0 or no pclkin seren = 0 or no pclkin sleep = 0, seren = 1 autos = high pwdn = high, power-on
37 MAX9273 22-bit gmsl serializer with coax or stp cable drive configuration link the control channel can operate in a low-speed mode called configuration link in the absence of a clock input. this allows a microprocessor to program configura - tion registers before starting the video link. an internal oscillator provides the clock for configuration link. set clinken = 1 on the serializer to enable configuration link. configuration link is active until the video link is enabled. the video link overrides the configuration link and attempts to lock when seren = 1. link startup procedure table 10 lists the start-up procedure for video-display applications. table 11 lists the startup procedure for image-sensing applications. the control channel is avail - able after the video link or the configuration link is estab - lished. if the deserializer powers up after the serializer, the control channel becomes unavailable until 2ms after power-up. applications information prbs test the serializer includes a prbs pattern generator that works with bit-error verification in the deserializer. to run the prbs test, set prbsen = 1 (0x04, d5) in the deserial - izer and then in the serializer. to exit the prbs test, set prbsen = 0 (0x04, d5) in the serializer. error generator the serializer contains an error generator that enables repeatable testing of the error-detection/correction fea - tures of the gmsl link. register 0x11 stores the configu - ration bits for the error generator. a f c sets the error- generation rate, type of errors, and the total number of errors. the error generator is off by default. dual c control usually systems have one f c to run the control channel, located on the serializer side for video-display appli - cations or on the deserializer side for image-sensing applications. however, a f c can reside on each side simultaneously and trade off running the control channel. in this case, each f c can communicate with the serializer and deserializer and any peripheral devices. contention occurs if both f cs attempt to use the control channel at the same time. it is up to the user to prevent this contention by implementing a higher-level protocol. in addition, the control channel does not provide arbitra - tion between i 2 c masters on both sides of the link. an acknowledge frame is not generated when communica - tion fails due to contention. if communication across the serial link is not required, the f cs can disable the forward and reverse control channel using the fwdccen and revccen bits (0x04, d[1:0]) in the serializer/deserial - izer. communication across the serial link is stopped and contention between f cs cannot occur. as an example of dual f c use in an image-sensing appli - cation, the serializer can be in sleep mode, waiting for wake-up by the f c on the deserializer side. after wake- up, the serializer-side f c assumes master control of the serializers registers. jitter-filtering pll in some applications, the clock input (pclkin) includes noise, which reduces link reliability. the clock input has a programmable narrowband jitter-filter pll that attenuates frequencies higher than 100khz (typ). enable the jitter- filter by setting enjitfilt = 1 (0x05, d6). pclkin spread tracking the serializer can operate with a spread pclkin signal. when using a spread pclkin signal, disable the jitter- filter by setting enjitfilt = 0 (0x05, d6). do not exceed the spread limitations in table 7 and keep modulation less than 40khz. in addition, turn off spread spectrum in the serializer/deserializer. the serializer/deserializer track the spread on pclkin. changing the clock frequency it is recommended that the serial link be enabled after the video clock (f pclkin ) and the control-channel clock (f uart /f i2c ) are stable. when changing clock frequency, stop the video clock for 5 f s, apply the clock at the new frequency, then restart the serial link or toggle seren. on-the-fly changes in clock frequency are possible if the new frequency is immediately stable and without glitches. the reverse control channel remains unavail - able for 350 f s after serial link start or stop. when using the uart interface, limit on-the-fly changes in f uart to factors of less than 3.5 at a time to ensure that the device recognizes the uart sync pattern. for example, when lowering the uart frequency from 1mbps to 100kbps, first send data at 333kbps, then at 100kbps for reduction ratios of 3 and 3.333, respectively. fast detection of loss-of-synchronization a measure of link quality is the recovery time from loss-of- synchronization. the host can be quickly notified of loss- of-lock by connecting the deserializers lock output to the deserializers gpi input. if lock is lost, gpo on the
38 MAX9273 22-bit gmsl serializer with coax or stp cable drive serializer follows the transition of lock at gpi. if other sources also use the gpi input, the f c can implement a routine to distinguish between interrupts from loss-of- lock and normal interrupts. the control channel does not require an active video link and thus can always monitor lock. lock asserts for a synchronized video link but not for the configuration link. providing a frame sync (camera applications) the gpi/gpo provides a simple solution for camera applications that require a frame sync signal from the ecu (e.g., surround-view systems). connect the ecu frame sync signal to the gpi input and connect the gpo output to the camera frame sync input. gpi/gpo have a typical delay of 275 f s. skew between multiple gpi/gpo channels is maximum 115 f s. if a lower skew signal is required, connect the cameras frame sync input to one of the serializers gpios and use an i 2 c broadcast write command to change the gpio output state. this has a maximum skew of 1.5 f s, independent from the used i 2 c bit rate . software programming of the device addresses the serializer and deserializer have programmable device addresses. this allows multiple gmsl devices, along with i 2 c peripherals, to coexist on the same control channel. the serializer device address is in register 0x00 of each device, while the deserializer device address is in register 0x01 of each device. to change a device address, first write to the device whose address changes (register 0x00 of the serializer for serializer device address change, or register 0x01 of the deserializer for deserializer device address change). then write the same address into the corresponding register on the other device (register 0x00 of the deserializer for serializer device address change, or register 0x01 of the serializer for deserializer device address change). three-level configuration inputs conf1 and conf0 are three-level inputs that control the serial interface configuration and power-up defaults. connect conf1or conf0 through a pullup resistor to iovdd to set a high level, a pulldown resistor to gnd to set a low level, or iovdd/2 or open to set a midlevel. for digital control, use three-state logic to drive the three- level logic inputs. configuration blocking the serializer can block changes to registers. set cfgblock to make all registers read only. once set, the registers remain blocked until the supplies are removed or until pwdn is low. compatibility with other gmsl devices the MAX9273 serializer is designed to pair with the max9272 deserializer, but interoperates with any gmsl deserializer. see table 12 for operating limitations. gpios the serializer has five open-drain gpios available when not used as data or configuration inputs. setting the gpio enable bits (register 0x0e) to 1 enables the gpios and internally connects the respective data or configuration input low. setting the gpio output bits to 0 pulls the output low, while setting the bits to 1 leaves the output undriven, and pulled high through internal/external pullup resistors. the gpio input buffers are enabled when the gpio is enabled. the input states are stored in register 0x10. set gpio_out to 1 when using a gpio_ as an input. table 12. MAX9273 feature compatibility MAX9273 feature gmsl deserializer hsync/vsync encoding if feature not supported in deserializer, must be turned off in the serializer. hamming-code error correction if feature not supported in deserializer, must be turned off in the serializer. i 2 c-to-i 2 c if feature not supported in deserializer, must use uart-to-i 2 c or uart-to-uart. crc error detection if feature not supported in deserializer, must be turned off in the serializer. double input if feature not supported in deserializer, data is output as a single word at half the input frequency. coax if feature not supported in deserializer, must connect unused serial input through 200nf and 50 i in series to avdd and set the reverse control-channel amplitude to 100mv. i 2 s encoding if supported in the deserializer, disable i 2 s in the deserializer.
39 MAX9273 22-bit gmsl serializer with coax or stp cable drive internal input pulldowns the control and configuration inputs (except three-level inputs) include a pulldown resistor to gnd. external pull - down resistors are not needed. choosing i 2 c/uart pullup resistors the i 2 c and uart open-drain lines require a pullup resistor to provide a logic-high level. there are tradeoffs between power dissipation and speed, and a compro - mise may be required when choosing pullup resistor values. every device connected to the bus introduces some capacitance even when the device is not in opera - tion. i 2 c specifies 300ns rise times (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the i 2 c specifications in the ac electrical characteristics table for details). to meet the fast-mode rise-time require - ment, choose the pullup resistors so that rise time t r = 0.85 x r pullup x c bus < 300ns. the waveforms are not recognized if the transition time becomes too slow. the serializer supports i 2 c/uart rates up to 1mbps (uart- to-i 2 c mode) and 400kbps (i 2 c-to-i 2 c mode). ac-coupling ac-coupling isolates the receiver from dc voltages up to the voltage rating of the capacitor. capacitors at the serializer output and at the deserializer input are needed for proper link operation and to provide protection if either end of the cable is shorted to battery. ac-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. selection of ac-coupling capacitors voltage droop and the digital sum variation (dsv) of trans - mitted symbols cause signal transitions to start from dif - ferent voltage levels. because the transition time is fixed, starting the signal transition from different voltage levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the cml/coax receiver termination resistor (r tr ), the cml/coax driver termination resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant for four equal-value series capacitors is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission line impedance (usually 100 i differential, 50 i single-ended). this leaves the capacitor selection to change the system time constant. use 0.2 f f or larger high-frequency surface-mount ceramic capacitors, with sufficient voltage rating to withstand a short to battery, to pass the lower speed reverse control-channel signal. use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. power-supply circuits and bypassing the serializer uses an avdd and dvdd of 1.7v to 1.9v. all inputs and outputs, except for the serial output, derive power from an iovdd of 1.7v to 3.6v that scales with iovdd. proper voltage-supply bypassing is essential for high-frequency circuit stability. power-supply table power-supply currents shown in the electrical characteristics table are the sum of the currents from avdd, dvdd, and iovdd. typical currents from the individual power supplies are shown in table 13 . cables and connectors interconnect for cml typically has a differential imped - ance of 100 i . use cables and connectors that have matched differential impedance to minimize impedance discontinuities. coax cables typically have a characteristic impedance of 50 i (contact the factory for 75 i operation). table 14 lists the suggested cables and connectors used in the gmsl link. table 14. suggested connectors and cables for gmsl table 13. typical power-supply currents (using worst-case input pattern) supplier connector cable type rosenberger 59s2ax-400a5-y rg174 coax jae mx38-ff a-bw-lxxxxx stp nissei gt11l-2s f-2wme awg28 stp rosenberger d4s10a-40ml5-z dacar 538 stp pclk (mhz) avdd (ma) dvdd (ma) iovdd (ma) 25 29.5 9.4 0.2 50 34.9 14.4 0.3
40 MAX9273 22-bit gmsl serializer with coax or stp cable drive figure 34. human body model esd test circuit figure 35. iec 61000-4-2 contact discharge esd test circuit figure 36. iso 10605 contact discharge esd test circuit board layout separate the lvcmos logic signals and cml/coax high- speed signals to prevent crosstalk. use a four-layer pcb with separate layers for power, ground, cml/coax, and lvcmos logic signals. layout pcb traces close to each other for a 100 i differential characteristic impedance. the trace dimensions depend on the type of trace used (microstrip or stripline). note that two 50 i pcb traces do not have 100 i differential impedance when brought close togetherthe impedance goes down when the traces are brought closer. use a 50 i trace for the single- ended output when driving coax. route the pcb traces for differential cml in parallel to maintain the differential characteristic impedance. avoid vias. keep pcb traces that make up a differential pair equal length to avoid skew within the differential pair. esd protection esd tolerance is rated for human body model, iec 61000-4-2, and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic systems. the serial outputs are rated for iso 10605 esd protection and iec 61000-4-2 esd protection. all pins are tested for the human body model. the human body model discharge components are c s = 100pf and r d = 1.5k i ( figure 34 ). the iec 61000-4-2 discharge compo - nents are c s = 150pf and r d = 330 i ( figure 35 ). the iso 10605 discharge components are c s = 330pf and r d = 2k i ( figure 36 ). storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1mi r d 1.5ki c s 100pf c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330i storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2ki c s 330pf
41 MAX9273 22-bit gmsl serializer with coax or stp cable drive table 15. register table (see table 1 ) register address bits name value function default value 0x00 d[7:1] serid xxxxxxx serializer device address. 1000000 d0 cfgblock 0 normal operation. 0 1 registers 0x00 to 0x1f are read only. 0x01 d[7:1] desid xxxxxxx deserializer device address. 1001000 d0 0 reserved. 0 0x02 d[7:5] ss 000 no spread spectrum. 000 001 0.5% spread spectrum. 010 1.5% spread spectrum. 011 2% spread spectrum. 100 no spread spectrum. 101 1% spread spectrum. 110 3% spread spectrum. 111 4% spread spectrum. d4 1 reserved. 1 d[3:2] prng 00 12.5mhz to 25mhz pixel clock. 11 01 25mhz to 50mhz pixel clock. 10 automatically detect the pixel clock range. 11 automatically detect the pixel clock range. d[1:0] srng 00 0.5 to 1gbps serial-bit rate. 11 01 1 to 2gps serial-bit rate. 10 automatically detect serial-bit rate. 11 automatically detect serial-bit rate. 0x03 d[7:6] autofm 00 calibrate spread-modulation rate only once after locking. 00 01 calibrate spread-modulation rate every 2ms after locking. 10 calibrate spread-modulation rate every 16ms after locking. 11 calibrate spread-modulation rate every 256ms after locking. d[5:0] sdiv 000000 autocalibrate sawtooth divider. 000000 xxxxxx manual sdiv setting. see the manual programming of the spread-spectrum divider section.
42 MAX9273 22-bit gmsl serializer with coax or stp cable drive table 15. register table (see table 1 ) (continued) register address bits name value function default value 0x04 d7 seren 0 disable serial link. power-up default when autos = high. reverse control-channel communication remains unavailable for 350 f s after the serializer starts/stops the serial link. 0, 1 1 enable serial link. power-up default when autos = low. reverse control-channel communication remains unavailable for 350 f s after the serializer starts/stops the serial link. d6 clinken 0 disable configuration link. 0 1 enable configuration link. d5 prbsen 0 disable prbs test. 0 1 enable prbs test. d4 sleep 0 normal mode. 0 1 activate sleep mode. d[3:2] inttype 00 local control channel uses i 2 c when i2csel = 0. 00 01 local control channel uses uart when i2csel = 0. 10, 11 local control channel disabled. d1 revccen 0 disable reverse control channel from deserializer (receiving). 1 1 enable reverse control channel from deserializer (receiving). d0 fwdccen 0 disable forward control channel to deserializer (sending). 1 1 enable forward control channel to deserializer (sending). 0x05 d7 i2cmethod 0 i 2 c conversion sends the register address when converting uart to i 2 c. 0 1 disable sending of i 2 c register address when converting uart-to-i 2 c (command-byte -only mode). d6 enjitfilt 0 jitter filter disabled. 0 1 jitter filter active. d[5:4] prbslen 00 continuous prbs length. 00 01 9.83mbit prbs length. 10 167.1mbit prbs length. 11 1341.5mbit prbs length. d[3:2] 00 reserved. 00 d1 enwaken 0 disable wake-up receiver. 0 1 enable out- wake-up receiver during sleep mode. d0 enwakep 0 disable wake-up receiver. 1 1 enable out- wake-up receiver during sleep mode.
43 MAX9273 22-bit gmsl serializer with coax or stp cable drive table 15. register table (see table 1 ) (continued) register address bits name value function default value 0x06 d[7:4] cmllvl 0000 do not use. 1000, 1010 0001 do not use. 0010 100mv output level. 0011 150mv output level. 0100 200mv output level. 0101 250mv output level. 0110 300mv output level 0111 350mv output level. 1000 400mv output level. power-up default when twisted-pair output is selected (table 9). 1001 450mv output level 1010 500mv output level. power-up default when coax output is selected (table 9). 1011 do not use. 1100 do not use. 1101 do not use. 1110 do not use. 1111 do not use. d[3:0] preemp 0000 preemphasis off. 0000 0001 -1.2db preemphasis. 0010 -2.5db preemphasis. 0011 -4.1db preemphasis. 0100 -6.0db preemphasis. 0101 do not use. 0110 do not use. 0111 do not use. 1000 1.1db preemphasis. 1001 2.2db preemphasis. 1010 3.3db preemphasis. 1011 4.4db preemphasis. 1100 6.0db preemphasis. 1101 8.0db preemphasis. 1110 10.5db preemphasis. 1111 14.0db preemphasis.
44 MAX9273 22-bit gmsl serializer with coax or stp cable drive table 15. register table (see table 1 ) (continued) register address bits name value function default value 0x07 d7 dbl 0 single-input mode. 0 1 double-input mode. d6 drs 0 high data-rate mode. 0 1 low data-rate mode. d5 bws 0 24-bit mode. 0 1 32-bit mode. d4 es 0 input data latched on rising edge of pclkin. power-up default determined by conf1 and conf0 (table 9). do not change this value while the pixel clock is running. 0, 1 1 input data latched on falling edge of pclkin. power-up default determined by conf1 and conf0 (table 9). do not change this value while the pixel clock is running. d3 0 reserved. 0 d2 hven 0 hs/vs encoding disabled. 0 1 hs/vs encoding enabled. d[1:0] edc 00 1-bit parity error detection (gmsl compatible). 00 01 6-bit crc error detection. 10 6-bit hamming code (single-bit error correct, double-bit error detect) and 16- word interleaving. 11 do not use. 0x08 d7 invvs 0 no vs or din0 inversion. 0 1 invert vs when hven = 1. invert din0 when hven = 0. do not use if dbl = 0 in the serializer and dbl = 1 in the deserialize r. d6 invhs 0 no hs or din1 inversion 0 1 invert hs when hven = 1. invert din1 when hven = 0. do not use if dbl = 0 in the serializer and dbl = 1 in the deserializer. d[5:0] 000000 reserved. 000000 0x09 d[7:1] i2csrca xxxxxxx i 2 c address translator source a. 0000000 d0 0 reserved. 0 0x0a d[7:1] i2cdsta xxxxxxx i 2 c address translator destination a. 0000000 d0 0 reserved. 0 0x0b d[7:1] i2csrcb xxxxxxx i 2 c address translator source b. 0000000 d0 0 reserved. 0
45 MAX9273 22-bit gmsl serializer with coax or stp cable drive table 15. register table (see table 1 ) (continued) register address bits name value function default value 0x0c d[7:1] i2cdstb xxxxxxx i 2 c address translator destination b. 0000000 d0 0 reserved. 0 0x0d d7 i2clocack 0 acknowledge not generated when forward channel is not available. 1 1 i 2 c-to-i 2 c slave generates local acknowledge when forward channel is not available. d[6:5] i2cslvsh 00 352ns/117ns i 2 c setup/hold time. 01 01 469ns/234ns i 2 c setup/hold time. 10 938ns/352ns i 2 c setup/hold time. 11 1046ns/469ns i 2 c setup/hold time. d[4:2] i2cmstbt 000 8.47kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 101 001 28.3kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 010 84.7kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 011 105kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 100 173kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 101 339kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 110 533kbps (typ) i 2 c-to-i 2 c master bit-rate setting. 111 837kbps (typ) i 2 c-to-i 2 c master bit-rate setting. d[1:0] i2cslvto 00 64 f s (typ) i 2 c-to-i 2 c slave remote timeout. 10 01 256 f s (typ) i 2 c-to-i 2 c slave remote timeout. 10 1024 f s (typ) i 2 c-to-i 2 c slave remote timeout. 11 no i 2 c-to-i 2 c slave remote timeout. 0x0e d7 dis_rev_p 0 out+ reverse channel receiver enabled. 0 1 out+ reverse channel receiver disabled. d6 dis_rev_n 0 out- reverse channel receiver enabled. 1 1 out- reverse channel receiver disabled. d5 gpio5en 0 disable gpio5. 0 1 enable gpio5. d4 gpio4en 0 disable gpio4. 0 1 enable gpio4. d3 gpio3en 0 disable gpio3. 0 1 enable gpio3. d2 gpio2en 0 disable gpio2. 0 1 enable gpio2. d1 gpio1en 0 disable gpio1. 1 1 enable gpio1. d0 0 reserved. 0
46 MAX9273 22-bit gmsl serializer with coax or stp cable drive table 15. register table (see table 1 ) (continued) register address bits name value function default value 0x0f d[7:6] 11 reserved. 11 d5 gpio5out 0 set gpio5 low. 1 1 set gpio5 high. d4 gpio4out 0 set gpio4 low. 1 1 set gpio4 high. d3 gpio3out 0 set gpio3 low. 1 1 set gpio3 high. d2 gpio2out 0 set gpio2 low. 1 1 set gpio2 high. d1 gpio1out 0 set gpio1 low. 1 1 set gpio1 high. d0 setgpo 0 set gpo low. 0 1 set gpo high. 0x10 d[7:6] 00 reserved. 00 d5 gpio5in 0 gpio5 is low. 1 (read only) 1 gpio5 is high. d4 gpio4in 0 gpio4 is low. 1 (read only) 1 gpio4 is high. d3 gpio3in 0 gpio3 is low. 1 (read only) 1 gpio3 is high. d2 gpio2in 0 gpio2 is low. 1 (read only) 1 gpio2 is high. d1 gpio1in 0 gpio1 is low. 1 (read only) 1 gpio1 is high. d0 gpo_l 0 gpo is set low. 0 (read only) 1 gpo is set high. 0x11 d[7:6] errgrate 00 generate an error every 2560 bits. 00 01 generate an error every 40,960 bits. 10 generate an error every 655,360 bits. 11 generate an error every 10,485,760 bits. d[5:4] errgtype 00 generate single-bit errors. 00 01 generate 2 (8b/10b) symbol errors. 10 generate 3 (8b/10b) symbol errors. 11 generate 4 (8b/10b) symbol errors. d[3:2] errgcnt 00 continuously generate errors. 00 01 16 generated errors. 10 128 generated errors. 11 1024 generated errors. d1 errgper 0 disable periodic error generation. 0 1 enable periodic error generation. d0 errgen 0 disable error generator. 0 1 enable error generator.
47 MAX9273 22-bit gmsl serializer with coax or stp cable drive table 15. register table (see table 1 ) (continued) register address bits name value function default value 0x12 d[7:0] 01000000 reserved. 01000000 0x13 d[7:0] 00100010 reserved 00100010 0x14 d[7:0] xxxxxxxx reserved. 00000000 (read only) 0x15 d7 cxtp 0 cxtp input is low. 0 (read only) 1 cxtp input is high. d6 i2csel 0 input is high. 0 (read only) 1 input is low. d5 lccen 0 input is high. 0 (read only) 1 input is low. d[4:2] 000 reserved. 000 (read only) d1 outputen 0 output disabled. 0 (read only) 1 output enabled. d0 pclkdet 0 valid pclkin detected. 0 (read only) 1 valid pclkin not detected. 0x16 d[7:0] xxxxxxxx reserved. 00000000 (read only) 0x17 d[7:0] xxxxxxxx reserved. 00000000 (read only) 0x1e d[7:0] id 00001011 device identifier (MAX9273 = 0x0b). 00001011 (read only) 0x1f d[7:5] 000 reserved. 000 (read only) d4 caps 0 not hdcp capable. 0 (read only) 1 hdcp capable. d[3:0] revision xxxx device revision. (read only)
48 MAX9273 22-bit gmsl serializer with coax or stp cable drive ordering information /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: cmos typical application circuit part temp range pin-package MAX9273gtl/v+ -40 n c to +105 n c 40 tqfn-ep* package type package code outline no. land pattern no. 40 tqfn-ep t4066+3 21-0141 90-0054 gpi rx /sda /edc tx /scl /es tx / scl lock int ms rx / sda to peripherals dout0?dout21 cx /t p pclkin note: not all pullup/pulldown resistors are shown. see pin description for details. video-display application tx rx gpo ms out+ out- gpu ecu conf1 pclkin din0?din21 conf0 rgbhv pclk pclk rgbhv display uart in+ in- MAX9273 max9272
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, inc. 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 49 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products inc. revision history revision number revision date description pages changed 0 6/12 initial release MAX9273 22-bit gmsl serializer with coax or stp cable drive

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